1. Field of the Invention
This invention relates to circuit placement and particularly to methods for producing optimal timing and improved wireability when determining circuit placement.
2. Description of Background
Before our invention of methods for combining improved timing with wireability, we developed in particular to circuit placement to improve initial placement of circuits and timing driven placement of circuits which we will describe herein. Chip design is a multi-variate design optimization problem. To enable ASIC and semi-custom chip designs to meet their design targets, a number of different design resources (architecture choices, logic synthesis, chip floorplanning, automated placement, circuit power level selection, buffer insertion, timing optimization logic transforms, etc) are brought to bear and expended in a sequence of design optimization steps and iterative feedback loops to achieve design closure.
The traditional methodology approach to chip design optimization and target convergence has involved an insular sequential application of design resources directed to achieve the greatest immediate improvement in the design state. Thus, design resources are applied in an amount and in an order that only marginally accounts for the interactions among those design resources. Depending on their nature, these interactions can promote or inhibit the convergence of the chip design to its design targets.
With increasing integration levels and signal frequencies, the interactions among design resources have become more significant. Designing future chips without regard to the synergistic application of design resources, will become an increasingly frustrating endeavor. Chip design schedules will lengthen, and some design targets will be regarded as unachievable even though a solution may exist. Thus, improvement is needed in the processes for chip design.